Lightweight and Tunable Soft Error Resilience for Protecting Caches and Memory against 2-Bit Errors. Shao-Yu Huang, Jungi Jeong, Hiroshi Sasaki, Changhee Jung. In Proceedings of the 47th IEEE Symposium on Real-Time Systems (RTSS), 2026 (to appear).
Teapot: Efficiently Uncovering Spectre Gadgets in COTS Binaries. Fangzheng Lin, Zhongfa Wang, Hiroshi Sasaki. In Proceedings of the 2025 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2025. (acceptance rate: 312/1061=29.4%)
RAPLET: Demystifying Publish/Subscribe Latency for ROS Applications. Keisuke Nishimura, Takahiro Ishikawa, Hiroshi Sasaki, Shinpei Kato. In Proceedings of the 27th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2021. (acceptance rate: 18/42=42.9%)
Practical Byte-Granular Memory Blacklisting using Califorms.
Hiroshi Sasaki, Miguel A. Arroyo, M. Tarek Ibn Ziad, Koustubha Bhat, Kanad Sinha, Simha Sethumadhavan.
In Proceedings of the 52nd IEEE/ACM International Symposium on Microarchitecture (MICRO), 2019. (acceptance rate: 80/345=23.2%)
IEEE Micro Top Picks Honorable Mention
Why Do Programs Have Heavy Tails? Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan. In Proceedings of the 2017 IEEE International Symposium on Workload Characterization (IISWC), 2017. (acceptance rate: 23/83=27.7%)
Characterization and Mitigation of Power Contention across Multiprogrammed Workloads. Hiroshi Sasaki, Alper Buyuktosunoglu, Augusto Vega, Pradip Bose. In Proceedings of the 2016 IEEE International Symposium on Workload Characterization (IISWC), 2016. (acceptance rate: 21/69=30.4%)
A Scalability Analysis of Many Cores and On-Chip Mesh Networks on the TILE-Gx Platform. Ye Liu, Hiroshi Sasaki, Shinpei Kato, Masato Edahiro. In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2016.
Runtime Multi-Optimizations for Energy Efficient On-Chip Interconnections. Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura. In Proceedings of the 33nd IEEE International Conference on Computer Design (ICCD), 2015. (poster presentation)
A Flexible Hardware Barrier Mechanism for Many-Core Processors. Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, Koji Inoue. In Proceedings of the 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 2015. (acceptance rate: 108/318=33.9%)
Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems. Satoshi Imamura, Hiroshi Sasaki, Koji Inoue. In Proceedings of the 32nd IEEE International Conference on Computer Design (ICCD), 2014. (acceptance rate: 63/202=31.2%)
Power and Performance Characterization and Modeling of GPU-Accelerated Systems. Yuki Abe, Hiroshi Sasaki, Shinpei Kato, Koji Inoue, Masato Edahiro, Martin Peres. In Proceedings of the 28th IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2014. (acceptance rate: 114/541=21.1%)
Coordinated Power-Performance Optimization in Manycores.
Hiroshi Sasaki, Satoshi Imamura, Koji Inoue.
In Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT), 2013. (acceptance rate: 36/208=17.3%)
IEEE Computer Society Japan Chapter Young Author Award 2013
McRouter: Multicast within a Router for High Performance Network-on-Chips. Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura. In Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT), 2013. (acceptance rate: 36/208=17.3%)
Power and Performance of GPU-Accelerated Systems: A Closer Look. Yuki Abe, Hiroshi Sasaki, Shinpei Kato, Koji Inoue, Masato Edahiro, Martin Peres. In Proceedings of the 2013 IEEE International Symposium on Workload Characterization (IISWC), 2013. (poster presentation)
Line Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality. Keitarou Oka, Hiroshi Sasaki, Koji Inoue. In Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013. (acceptance rate: 97/311=31.2%)
SMYLEref: A Reference Architecture for Manycore-Processor SoCs. Masaaki Kondo, Son-Truong Nguyen, Tomoya Hirao, Takeshi Soga, Hiroshi Sasaki, Koji Inoue. In Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013. (invited paper)
Scalability-Based Manycore Partitioning. Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura. In Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012. (acceptance rate: 39/207=18.8%)
Performance Evaluation of 3D Stacked Multi-Core Processors with Temperature Consideration. Takaaki Hanada, Hiroshi Sasaki, Koji Inoue, Kazuaki J. Murakami. In Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), 2012.
Cooperative Shared Resource Access Control for Low-Power Chip Multiprocessors. Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura. In Proceedings of the 14th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2009. (acceptance rate: 72/208=34.6%)
An Intra-Task DVFS Technique Based on Statistical Analysis of Hardware Events. Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura. In Proceedings of the 4th ACM International Conference on Computing Frontiers (CF), 2007. (acceptance rate: 28/56=50.0%)
Energy-Efficient Dynamic Instruction Scheduling Logic through Instruction Grouping. Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura. In Proceedings of the 2006 ACM International Symposium on Low Power Electronics and Design (ISLPED), 2006. (acceptance rate: 75/214=35.0%)
Exploiting Decompression Latency for Covert Channels in Inter-Line-Compressed LLCs. David K. Oh, Hiroshi Sasaki. IEEE Computer Architecture Letters (CAL), pp.xx–xx, 2026 (accepted for publication).
Improving Indirect Branch Prediction in Interpreters via Hardware/Software Co-Design. Linfeng Zheng, Hiroshi Sasaki. IEEE Computer Architecture Letters (CAL), pp.xx–xx, 2026 (accepted for publication).
Hardware-Accelerated Parallel Wrong-Path Execution for Spectre Gadget Detection. Fangzheng Lin, Zeyu Gao, Yanru Lin, Yangyu Chen, Hiroshi Sasaki. IEEE Computer Architecture Letters (CAL), Vol.25, Issue 1, pp.239–242, June 2026 (published in June 2026).
Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs. Satoshi Imamura, Yuichiro Yasui, Koji Inoue, Takatsugu Ono, Hiroshi Sasaki, Katsuki Fujisawa. IEICE Transactions on Information and Systems, Vol.E101-D, No.9, pp.2247–2257, Sep. 2018.
Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors. Teruo Tanimoto, Takatsugu Ono, Koji Inoue, Hiroshi Sasaki. IEEE Computer Architecture Letters (CAL), Vol.16, Issue 2, pp.111–114, Jul-Dec 2017 (published in Mar 2017).
Heavy Tails in Program Structure. Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan. IEEE Computer Architecture Letters (CAL), Vol.16, Issue 1, pp.34–37, Jan-Jun 2017 (published in May 2016).
Mitigating Power Contention: A Scheduling Based Approach. Hiroshi Sasaki, Alper Buyuktosunoglu, Augusto Vega, Pradip Bose. IEEE Computer Architecture Letters (CAL), Vol.16, Issue 1, pp.60–63, Jan-Jun 2017 (published in May 2016).
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura. IEICE Transactions on Information and Systems, Vol.E99.D, No.12, pp.2881–2890, Dec. 2016.
Adaptive Data Compression on 3D Network-on-Chips. Yuan He, Hiroki Matsutani, Hiroshi Sasaki, Hiroshi Nakamura. IPSJ Transactions on Advanced Computing Systems, Vol.5, No.1, pp.80–87, Jan. 2012.
Energy-Efficient Dynamic Instruction Scheduling Logic through Instruction Grouping. Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura. IEEE Transactions on VLSI (TVLSI), Vol.17 Issue 6, pp.848–852, June 2009. (Transactions Briefs)
Power-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping. Satoshi Imamura, Yuichiro Yasui, Koji Inoue, Takatsugu Ono, Hiroshi Sasaki, Katsuki Fujisawa. High Performance Graph Data Management and Processing Workshop 2016 (HPGDMP), 2016. (held in conjunction with SC)
An Empirical Study on the NoC Architecture Based on Bidirectional Ring and Mesh Topologies. Jie Yin, Ye Liu, Shinpei Kato, Hiroshi Sasaki, Hiroaki Takada. 2016 Workshop on Multicore and Rack-scale Systems (MaRS), 2016. (held in conjunction with EuroSys)
Predict-More Router: A Low Latency NoC Router with More Route Predictions. Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura. In Proceedings of the 2013 IEEE International Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2013. (presented at Communication Architecture for Scalable Systems (CASS))
Power and Performance Analysis of GPU-Accelerated Systems. Yuki Abe, Hiroshi Sasaki, Martin Peres, Koji Inoue, Kazuaki Murakami, Shinpei Kato. 2012 Workshop on Power-Aware Computing and Systems (HotPower), 2012. (held in conjunction with OSDI)
Optimizing Power-Performance Trade-Off for Parallel Applications through Dynamic Core-Count and Frequency Scaling. Satoshi Imamura, Hiroshi Sasaki, Naoto Fukumoto, Koji Inoue, Kazuaki Murakami. 2nd Workshop on Runtime Environments/Systems, Layering, Virtualized Environments (RESoLVE), 2012. (held in conjunction with ASPLOS)
Efficient Barrier Synchronization for 2D Meshed NoC-Based Many-Core Processors. Lovic Gauthier, Farhad Mehdipour, Koji Inoue, Shinya Ueno, Hiroshi Sasaki. 17th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), 2012.
Power-Performance Modeling of Heterogeneous Cluster-Based Web Servers. Hiroshi Sasaki, Takatsugu Oya, Masaaki Kondo, Hiroshi Nakamura. In Proceedings of the 2009 20th IEEE/ACM International Conference on Grid Computing (Grid), 2009. (presented at Energy Efficient Grids, Clouds and Clusters Workshop (E2GC2))
Compiler Directed Fine Grain Power Gating for Leakage Power Reduction in Microprocessor Functional Units. Toshiya Komoda, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura. Workshop on Optimizations for DSP and Embedded Systems (ODES), 2009. (held in conjunction with CGO)
Improving Fairness, Throughput and Energy-Efficiency on a Chip Multiprocessor through DVFS. Masaaki Kondo, Hiroshi Sasaki, Hiroshi Nakamura. Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP), 2006. (held in conjunction with MICRO—Also in ACM SIGARCH Computer Architecture News, Vol.35, Issue 1, Mar. 2007)
Dynamic Instruction Cascading on GALS Microprocessor. Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2005.